內(nèi)容簡介：
本科畢業(yè)設(shè)計(jì) EDA技術(shù)設(shè)計(jì)多功能電子鐘
verilog hdl|電子鐘|多功能|EDA
文件格式：word
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論文正文共51頁。共24870個(gè)字符數(shù)（不計(jì)空格）。整套壓縮包大�。�600KB。
外文翻譯 Based on FPGA digital TV CSD filter to image signal format conversion（基于FPGA數(shù)字電視CSD濾波器對(duì)圖像信號(hào)格式轉(zhuǎn)換）。
摘要
隨著大規(guī)模集成電路技術(shù)和計(jì)算機(jī)技術(shù)的不斷發(fā)展，在涉及通信、國防、航天、醫(yī)學(xué)、工業(yè)自動(dòng)化、計(jì)算機(jī)應(yīng)用、儀器儀表等領(lǐng)域的電子系統(tǒng)設(shè)計(jì)工作中，EDA技術(shù)的含量正以驚人的速度上升;電子類的高新技術(shù)項(xiàng)目的開發(fā)也日益依賴于EDA技術(shù)的應(yīng)用。即使是普通的電子產(chǎn)品的開發(fā)，EDA技術(shù)常常使一些原來的技術(shù)瓶頸得以輕松突破，從而使產(chǎn)品的開發(fā)周期大為縮短、性能價(jià)格比大幅提高。不言而喻，EDA技術(shù)將迅速成為電子設(shè)計(jì)領(lǐng)域中的極其重要的組成部分
本實(shí)驗(yàn)闡述了基于EDA設(shè)計(jì)軟件Quartus II 提供的FPGA/CPLD開發(fā)集成環(huán)境，結(jié)合verilg hdl語言以及組合電路等來設(shè)計(jì)多功能數(shù)字鐘的方法。該數(shù)字鐘具有校時(shí)、校分、清零、保持、鬧鈴、秒表等功能。本實(shí)驗(yàn)用Verilog hdl語言實(shí)現(xiàn)了分頻、計(jì)數(shù)、等功能，并利用原理圖完成了計(jì)時(shí)模塊、報(bào)時(shí)模塊、譯碼顯示模塊、鬧鈴模塊、秒表模塊等的設(shè)計(jì)。通過按鍵可由正常計(jì)時(shí)狀態(tài)切換到鬧鈴狀態(tài)，鬧鈴模塊通過比較設(shè)定時(shí)間與實(shí)際時(shí)間，一致時(shí)觸發(fā)鈴聲。該數(shù)字鐘原理簡單，功能可根據(jù)需要繼續(xù)添加.具有功能多、操作簡單、性能可靠。
關(guān)鍵字： verilog hdl,電子鐘,多功能,EDA。
EDA multi-function electronic clock
Abstract ：Along with large scale integrated circuit technology and development of computer technology, communication, national defense, in which space, medical, industrial automation, computer application, instruments and other areas of electronic system design work, the content of EDA technology is developing at a breathtaking speed up; Electronics high-tech project development also more than benefit depends on EDA technology application. Even ordinary electronic product development, EDA technology often make some originally the technical bottleneck to break easily, so as to make the development of the product cycle is much shorter, performance to price increase. Self-evident, EDA will quickly become a technology in the field of electronic design of the most important components
It is presented based on the experiment EDA software Quartus II provides the FPGA/CPLD integrated development environment, combined with verilg HDL language and circuit design and multi-function combination of digital clock method. The digital clock with the school, the school to points when, reset, keep, and time on the hour, alarm, a stopwatch etc.
Function. This experiment with Verilog HDL language realized the points, counting, and comparison of the frequency response function and use principle diagram completed the timer modules, time module, decode display module, alarm module, a stopwatch module design. Through the buttons can be made of normal time state switch to alarm condition, alarm module by comparing with the actual time set time, consistent triggered when the bell ring. The digital clock simple principle, function can according to need to continue to add. Has the function is much, the operation is simple, reliable performance.
key word ：verilog hdl,electric clock,multifunctional,EDA.
目錄
摘 要 II
Abstract II
緒 論 1
第一章、本畢業(yè)設(shè)計(jì)的目的 2
第二章、FPGA/CPLD的特點(diǎn) 2
第三章、 設(shè)計(jì)要求說明 2
第四章、方案論證 4
4.1 根據(jù)設(shè)計(jì)要求完成以下功能模塊 4
4.1.1 實(shí)驗(yàn)數(shù)字鐘的計(jì)時(shí)功能 4
4.1.2 實(shí)現(xiàn)控制按鍵去抖動(dòng)功能 4
4.1.3 實(shí)現(xiàn)數(shù)字鐘的校時(shí)校分功能 4
4.1.4 實(shí)現(xiàn)數(shù)字鐘的清零、保持功能 4
4.1.5 要實(shí)現(xiàn)鬧鐘功能 4
4.1.6 增加秒表功能 5
4.2 電路整體設(shè)計(jì) 5
第五章 、 各子模塊設(shè)計(jì)原理 5
5.1 防抖動(dòng)程序 5
5.2 計(jì)時(shí)模塊 6
5.3 秒表功能模塊 13
5.4 校時(shí)功能模塊 18
5.5 鬧鐘功能模塊 23
第六章、切換模態(tài)、設(shè)置鬧鐘時(shí)間并消顫 30
第七章、引腳設(shè)置與仿真 30
第八章、實(shí)驗(yàn)中遇到問題 32
第九章、感想 32
參考文獻(xiàn)(References) 33
附 件1 33
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