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High-Speed Board Design Techniques電子書(shū)
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資料類(lèi)別
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電子電工軟件圖書(shū) |
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課程(專(zhuān)業(yè))
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High-Speed Board Design Techniques |
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關(guān)鍵詞
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High-Speed Board Design Techniques|高速電路板設(shè)計(jì) |
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適用年級(jí)
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大學(xué) |
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身份要求
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普通會(huì)員 |
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金 幣
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0 �。�金幣如何獲得？） |
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文件格式
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pdf |
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文件大小
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662K |
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發(fā)布時(shí)間
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2011-11-08 10:17:00 |
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預(yù)覽文件
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無(wú) |
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下載次數(shù)
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2 |
| 發(fā)布人 |
lj |
內(nèi)容簡(jiǎn)介：
High-Speed Board Design Techniques電子書(shū)，共40頁(yè)
The most important factor in the design of many systems today is speed. 66-MHz thru 200-MHz
processors are common; 233 and 266-MHz processors are becoming readily available. The demand
for high speed results from: a) the requirement that systems perform complex tasks in a time frame considered comfortable by humans; and b) the ability of component manufacturers to produce high-speed devices. An example of a) is the large amount of information that must be processed to perform even the most rudimentary computer animation. Currently, Programmable Array Logic (PAL®) devices are available with propagation delays of 4.5 ns, and complex PLDs such as MACH® have propagation delays of 5 ns. While this might seem fast, it is not the propagation delay that creates the potential for problems, but rather the fast edge rates needed to obtain the fast propagation delays. In the future, much faster devices will become available, with correspondingly faster edge rates.
......
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